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HT47C06L r-f type low voltage 8-bit mask mcu rev. 1.00 1 june 15, 2007 features operating voltage: 1.2v~2.2v eight bidirectional i/o lines on-chip 32khz~128khz rc oscillator (external r) rc type a/d converter watchdog timer 1k 16 program memory rom 32 8 data memory ram one time base (tb) one buzzer output (bz, bz ) one el carrier output one externally adjustable low voltage detector one lcd driver with 13 3or14 2 segments halt function and wake-up feature reduce power consumption two-level subroutine nesting bit manipulation instruction 16-bit table read instruction up to 31 s instruction cycle with128khz system clock 63 powerful instructions all instructions in one or two machine cycles 44-pin qfp package general description the HT47C06L is an 8-bit, high performance risc ar- chitecture microcontroller device specifically designed for applications that interface directly to analog signals, such as those from sensors. its single cycle instruction and two-stage pipeline architecture make it suitable for high speed applications. the advantages of low power consumption, i/o flexibility, timer functions, oscillator options, rc type a/d converter, lcd driver, halt and wake-up functions, enhance the versatility of these device to suit a wide range of resistor to frequency application possibilities such as sensor sig- nal processing, remote metering, and particularly suit- able for use as clinical thermometer mcu device. technical document tools information faqs application note
block diagram pin assignment HT47C06L rev. 1.00 2 june 15, 2007

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pad description pad name i/o function res i schmitt trigger reset input. active low pa0/bz pa1/bz i/o i/o bidirectional 2-bit input/output port. each bit can be a wake-up input. the pa0 and pa1 are pin-shared with the bz and bz , respectively. once the pa0 and pa1 are selected as buzzer driving outputs, the output signals come from an internal buzzer clock generator. software instructions determine the cmos output or schmitt trigger input with pull-high re - sistor (mask option). pa2/el i/o bidirectional 1-bit input/output port. this bit can be a wake-up input. the pa2 is pin-shared with the el carrier output. once the pa2 is selected as el carrier output, the output signal comes from an internal el carrier clock generator. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (mask option). pa3~pa7 i/o bidirectional 5-bit input/output port. each bit can be a wake-up input. software instructions determine the cmos output or schmitt trigger input with pull-high re - sistor (mask option). vss negative power supply, ground vcc, c1, c2 voltage doubler, vcc=2 vdd vcc: lcd power supply voltage, connect a capacitor between vcc and vss. c1, c2: switching pins for vcc, connect a capacitor between c1 and c2. com0~com1, com2/seg13 o the 1 / 3 lcd duty cycle configuration option will determine whether pin com2/seg13 is configured as a seg13 segment driver or as a common com2 output driver for the lcd panel. com0~com1 are the lcd common outputs. seg0~seg12 o lcd driver outputs for lcd panel segments. vdd positive power supply lvd low voltage detector. connect a resistor between vss and lvd. rcin i rc type a/d converter input pin for rc oscillation. rref o rc type a/d converter output pin for reference resistor oscillation. rsen o rc type a/d converter output pin for sensor resistor oscillation. osc1 osc2 system oscillator pin, connect a resistor between osc1 and osc2. trim1~trim2 i test mode input pin. let open in normal mode. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +2.5v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT47C06L rev. 1.00 3 june 15, 2007
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 1.2 1.5 2.2 v v cc lcd voltage vcc=2 vdd 2.4 3 4.4 v v lvd low voltage detector voltage *r lvd =30k 1.25 1.3 1.35 v i dd operating current 1.5v no load, f sys =32khz, a/d off, lvd disabled 10 20 a no load, f sys =32khz, a/d on, lvd disabled, *r=30k , *c=2200pf 30 60 a no load, f sys =128khz, a/d off, lvd disabled 15 30 a no load, f sys =128khz, a/d on, lvd disabled, *r=30k , *c=2200pf 35 70 a i lvd lvd current 1.5v lvd enabled 50 100 a i stb1 standby current ( lvd disabled, lcd off) 1.5v no load, system halt a/d off, lvd off 1 a i stb2 standby current (lcd on) 1.5v no load, f sys =32khz, a/d off, lvd disabled 510 a no load, f sys =128khz, a/d off, lvd disabled 816 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.8v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol1 i/o port sink current (pa0/bz, pa1/bz , pa2/el, pa3~pa7) 1.5v v ol =0.15v 0.5 0.8 ma i oh1 i/o port source current (pa0/bz, pa1/bz , pa2/el, pa3~pa7) 1.5v v oh =1.35v 0.3 0.6 ma i ol2 i/o port sink current (rref, rsen) 1.5v v rref, rsen =0.15v 47 ma i oh2 i/o port source current (rref, rsen) 1.5v v rref, rsen =1.35v 3 5 ma i ol3 common output sink current 1.5v v ol =0.3v (1 / 2 bias) 50 100 a i oh3 common output source current 1.5v v oh =2.7v(1 / 2 bias) 50 100 a i ol4 segment output sink current 1.5v v ol =0.3v (1 / 2 bias) 50 100 a i oh4 segment output source current 1.5v v oh =2.7v(1 / 2 bias) 50 100 a r ph pull-high resistance 1.5v v il =0v 75 150 300 k note: *r stands for the rc type a/d converter resistance *c stands for the rc type a/d converter capacitance *r lvd value may be different for different lots HT47C06L rev. 1.00 4 june 15, 2007
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 1.5v external r 25 154 khz t res external reset low pulse width 1.5v 100 s f ad a/d converter frequency 1.5v 50 khz HT47C06L rev. 1.00 5 june 15, 2007 * * * * * * * * * * * * % $ ' 5 6 * 6 = > ? % ' " $ % 6 * 6 = @ > % $ ' 5 6 * 6 = a > ? % ' " $ % 6 * 6 = > % $ ' 5 6 * 6 = a > ? % ' " $ % 6 * 6 = a > a a 4 & $ % ! 6 7 ' . # & $ " ' $ ( # 6 7 ' . execution flow functional description execution flow the HT47C06L system clock is derived from a built-in rc oscillator with external resistor. the system clock is internally divided into four non-overlapping clocks (t1, t2, t3 and t4). one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. this pipelining scheme ensures that instructions are ef - fectively executed in one cycle. exceptions to this are in - structions that change the contents of the program counter, such as subroutine calls or jumps, in which case, two cycles are required to complete the instruc- tion. program counter pc the 10-bit program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a maximum of 1024 addresses. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. mode program counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000 timer/event counter interrupt 0000000100 time base interrupt 0000001000 skip program counter + 2 loading pcl *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *9~*0: program counter bits #9~#0: instruction code bits s9~s0: stack register bits @7~@0: pcl bits
HT47C06L rev. 1.00 6 june 15, 2007 when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, etc., the microcontroller manages program control by loading the address corresponding to each in - struction. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the current instruction execution, is dis - carded and a dummy cycle replaces it while the proper instruction is obtained. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is avail - able for program control and is a readable and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory is used to store the program in - structions, which are to be executed. it also contains data, table information and interrupt entries, and is orga - nized into 1024 16 bits, addressed by the program counter and table pointer registers. certain locations within the program memory are re- served for special usage: location 000h this area is reserved for use by the chip reset for pro- gram initialization. after a chip reset is initiated, the program will jump to this location and begin execution. location 004h this area is reserved for the timer/event counter inter- rupt service program. if timer interrupt results from a timer/event counter a or b overflow, and if the inter - rupt is enabled and the stack is not full, the program will jump to this location and begin execution. location 008h this area is reserved for the time base interrupt ser - vice program. if a time base interrupt occurs, and if the interrupt is enabled and the stack is not full, the pro - gram will jump to this location and begin execution. table location any location within the program memory can be used as a look-up table where programmers can store fixed data. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh(08h). only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the tblh. the ta - ble higher-order byte (tblh) is a read only register. the table pointer (tblp) is a read/write register(07h), which indicates the table location. before accessing the table, the location must be placed in the tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words using the table read instruc - tion in the main routine and the isr simultaneously should be avoided. however, if the table read instruc - tion has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related in - structions need two cycles to complete the operation. these areas may function as normal program mem- ory depending upon the requirements. % 8 ( ' % 6 # ( $ ( 7 ( 0 $ ( # 6 ! ! 6 ; ( $ & . @ " 1 6 * ; 7 % 6 = 6 b ) & > $ % c 6 # 6 # % & 6 + ! 6 6 $ 6 * ( ! % 6
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HT47C06L rev. 1.00 7 june 15, 2007 stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into two levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the stack pointer will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but ac - knowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent two return ad - dresses is stored). data memory ram the data memory has a capacity of 52 8 bits and is di- vided into two functional groups: special function regis- ters and general- purpose data memory (32 8). most are read/write, but some are read only. the special function registers include the indirect address- ing register 0 (00h), the memory pointer register 0 (mp0; 01h), the indirect addressing register 1 (02h), the memory pointer register 1 (mp1;03h), the bank pointer (bp;04h), the accumulator (acc;05h), the program counter lower-order byte register (pcl;06h), the table pointer (tblp;07h), the table higher-order byte register (tblh;08h), the time base control register (tbc;09h), the status register (status;0ah), the interrupt control regis - ter 0 (intc;0bh), the i/o registers (pa;12h), i/o port con - trol register (pac;13h), the timer/event counter a higher-order byte register (tmrah; 20h), the timer/event counter a lower-order byte register (tmral; 21h), the timer/event counter control register (tmrc; 22h), the timer/event counter b higher-order byte register (tmrbh; 23h), the timer/event counter b lower-order byte register (tmrbl; 24h), the rc oscillator type a/d converter con - trol register (adcr; 25h). the remaining space before the 60h are reserved for fu - ture expanded usage and reading these location will re - turn the result 00h. the general-purpose data memory, addressed from 60h to 7fh, is used for data and control information under instruction command. all data memory areas can handle arithmetic, logic, in - crement, decrement and rotate operations. except for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instruction, respectively. they are also indirectly accessible through memory pointer registers (mp0;01h, mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration to [00h] and [02h] access data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly will return a result of 00h. writing indirectly results in no operation. / % # % 7 @ " 1 & % $ 6 % ! 4 = 6
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HT47C06L rev. 1.00 8 june 15, 2007 bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register the function of data movement between two indirect ad - dressing registers are not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers which can be used to access the data memory by com - bining corresponding indirect addressing registers. mp0 only can be applied to data memory, while mp1 can be applied to the data memory and the lcd display memory. accumulator the accumulator is closely related with operations car - ried out by the alu. it is mapped to location 05h of the data memory and is the place where all immediate re - sults from the alu are stored. data move ment between two data memory locations must pass through the accu - mulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but can also change the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flags. in addi - tion it should be noted that operations related to the status register may give different results from those intended. the to and pdf flags can only be changed by the watchdog timer overflow, system power-up, clearing the watchdog timer and execut - ing the halt instruction. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. interrupts the HT47C06L provides an internal timer/event counter interrupt and an internal time base interrupt. the inter - rupt control register (intc;0bh) contains the interrupt control bits to set the enable/disable and interrupt re - quest flags. once an interrupt subroutine is serviced, all other inter - rupts will be blocked by clearing the emi bit. this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval, but only the interrupt request flag is recorded. if another in- terrupt requires servicing while the program is in the in- terrupt service routine, the programmer should set the emi bit and the corresponding bit of the intc to allow in- terrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is en- abled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from be - coming full. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified locations in the pro -
HT47C06L rev. 1.00 9 june 15, 2007 gram memory. only the program counter is pushed onto the stack. if the contents of the register and status regis - ter (status) is altered by the interrupt service program which corrupts the desired control sequence, the con - tents must be saved first. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 4 of intc), caused by a timer a or timer b overflow. when the interrupt is enabled, and the stack is not full and the tf bit is set, a subroutine call to location 04h will occur. the related interrupt request flag (tf) will be reset and the emi bit cleared to disable further interrupts. the time base interrupt is initialized by setting the time base interrupt request flag (tbf; bit 5 of intc), caused by a regular time base signal. when the interrupt is en- abled, and the stack is not full and the tbf bit is set, a subroutine call to location 08h will occur. the related in- terrupt request flag (tbf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in- terrupt acknowledgments are held until the reti in- struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti in - struction may be invoked. reti will set the emi bit to en - able an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector timer/event counter interrupt 1 04h time base interrupt 2 08h oscillator configuration there is one external rc oscillator. one method to generating the system clock is using an external rc network. the halt mode turned off the system oscillator and ignores an external signal to con - serve power. if an rc oscillator is used, it requires that an external re - sistor is connected between osc1 and osc2. the rc oscillator provides the most cost effective solution. how - ever, the oscillation frequency may vary with vdd, tem - perature and process variations on the chip itself. it is therefore not suitable for applications involving timing sensitive operations or where accurate oscillator fre - quencies are required. watchdog timer wdt the wdt clock source (f s )isf sys . the timer is de signed to prevent software malfunctions or sequences from jump- ing to unknown locations with unpredictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. the halt instruction is executed, wdt still counts if f osc is on and can wake-up from halt mode due to the wdt time-out. the wdt overflow under normal operation will initialize a chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset wherein only the program counter and stack pointer are reset to zero. to clear the contents of the wdt, three methods are adopted. the first is an external hardware reset (a low level on the res pin), the second is via soft - ware instructions, and the third is via a halt instruc - tion. the software instruction is clr wdt. any execution of the clr wdt instruction will clear the wdt. the wdt may reset the chip due to time-out. the wdt time-out period ranges from f s /2 15 ~f s /2 16 . the clr wdt instruction only clears the last two-stage of the wdt. bit no. label function 0 emi controls the master or global interrupt (1=enabled; 0=disabled) 1 eti controls the timer/event counter interrupt (1=enabled; 0=disabled) 2 etbi controls the time base interrupt (1=enabled; 0=disabled) 3 unused bit, read as 0 4 tf timer/event counter interrupt request flag (1=active; 0=inactive) 5 tbf time base interrupt request flag (1=active; 0=inactive) 6~7 unused bit, read as 0 intc (0bh) register 6 & ' ( 7 7 $ system oscillator
HT47C06L rev. 1.00 10 june 15, 2007 multi-function timer the HT47C06L provides a multi-function timer for the wdt and time base but with different time-out periods. the multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from f sys . the multi-function timer also provides a selectable frequency signal (ranges from f s /2 3 to f s /2 6 ) for lcd driver circuits, and a selectable frequency signal (ranges from f s /2 2 to f s /2 5 ) for the buzzer output by op - tions. it is recommended to select a near 4khz signal to lcd driver circuits for proper display. time base tb the time base is used to supply a regular internal inter - rupt. its time-out period ranges from f s /2 8 to f s /2 15 by software programming. writing data to rt2, rt1 and rt0 (bits 2, 1, 0 of tbc;09h) yields various time-out periods. if a time base time-out occurs, the related inter - rupt request flag (tbf; bit 5 of intc) is set. but if the in - terrupt is enabled, and the stack is not full, a subroutine call to location 08h occurs. when the halt instruction is executed, the time base still works and can wake-up from halt mode if f osc is on. if the tbf is set to 1 be - fore entering the halt mode, the wake-up function will be disabled. rt2 rt1 rt0 time base divided factor 000 2 8 001 2 9 010 2 10 011 2 11 100 2 12 101 2 13 110 2 14 111 2 15 power down operation halt the halt mode is initialized by the halt instruction and results in the following: the f osc and f sys will still work or stop depending on the lcd option, but t1 will be turned off. the contents of the on-chip ram and registers remain unchanged. the wdt will be cleared and resume counting. all i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the lcd driver can be turned off or on depending on the lcd option. the time base will stop or keep running depending on the lcd option. port a wake-up and external interrupt wake-up methods can be considered as a continuation of normal execu - tion. awakening from an i/o port stimulus, the program will resume execution at the next instruction. if awaken - ing from an external interrupt, two possibilities may occur. if the external interrupt is disabled or the external interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the external interrupt is enabled and the stack is not full, a regular in - terrupt response takes place. if an external interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the re - lated interrupt will be disabled. if the wake-up results from an external interrupt ac - knowledge signal, the actual interrupt subroutine execu - tion will be delayed by more than one cycle. however, if the wake-up results in the next instruction execution fol - lowing the halt , the execution will be performed im- mediately. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt mode. reset there are three ways in which a reset may occur. res reset during normal operation res reset during halt mode wdt time-out reset during normal operation the wdt time-out reset during halt mode is different from other chip reset conditions, since it can perform a warm reset that just resets the program counter and stack pointer leaving the other circuits in their original state. some registers remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by exam - ining the pdf and to flags, the program can distinguish between different chip resets . @ & $ % 6 ( 8 ( ) % 6 6 6 6 6 6 6 6 6 $ 6 6 " ? e @ ; ( $ 6 % & ' 7 % + + 4 & $ % ! 6 7 ' . 6 = + , > 6 ( 8 % 6 + 9 +
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HT47C06L rev. 1.00 11 june 15, 2007 to pdf reset conditions 0 0 system power-up u u res or lvr reset during normal operation 01 res reset or lvr reset wake-up from halt mode 1 u wdt time-out during normal operation 1 1 wdt wake-up from halt mode note: u stands for unchanged the following table indicates the way in which the vari - ous functional units are affected after a reset occurs. item condition after reset program counter reset to 000h interrupts all interrupts will be disabled prescaler, divider all timer counter prescaler, divider will be cleared wdt, time base clear after master reset, wdt be - gins counting timer/event counter all timer counters will be turned off input/output ports all i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack $ * * 6 * ( ! % @ " $ 5 ( 1 6 6 % & % $ : ! 6 % & % $ : * 7 ) % & % $ / * b % @ # 6 % $ % ' $ ( # * @ ; ( $ 6 ( 1 1 7 % " # $ % + , * ( ! % @ " $ % & % $ : * ? $ % # 7 the states of the registers are summarized in the following table: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h* tblp xxxx xxxx uuuu uuuu uuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tbc ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu tmrah xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc -000 1--- -000 1--- -000 1--- -000 1--- -uuu u--- tmrbh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr ---x 0000 ---x 0000 ---x 0000 ---x 0000 ---u uuuu note: * refers to warm reset u means unchanged x means unknown
HT47C06L rev. 1.00 12 june 15, 2007 * 4 & $ % ! 6 7 ' . 6 = + , > * * * " 7 & % 6 : ( ) $ 5 % & " % ! % # $ ) % 6 # $ 7 * ( ! % % 8 % # $ 6 ' " # $ % = 6 ; ( $ 6 * ( ! % 6 > * ( ! % % 8 % # $ 6 ' " # $ % % 7 ) 6 % ( & $ % = 6 ; ( $ 6 * ( ! % 6
> $ 6
" & % 7 ) 8 % + 7 b * * * - * * * = 6
( $ @ > 6 ) % # $ 7 1 . . 9 . 6 7 ' . timer/event counter timer/event counter one 16-bit timer/event counter or rc type a/d con - verter is implemented in the HT47C06L. the adc/tm bit (bit 1 of adcr register) determines whether timer a and timer b are composed of one 16-bit timer/event counter or composed of an rc type a/d converter. the tmral, tmrah, tmrbl, tmrbh composed of one 16-bit timer/event counter, when adc/tm bit is 0 . the tmrbl and tmrbh are timer/event counter preload registers for low er-order byte and higher-order byte respectively. the timer/event counter clock source comes from system clock (f sys ) or external source (a/d clock from pad:rcin). the external clock input allows the user to count external events, count external rc type a/d clock, measure time in - tervals or pulse widths, or generate an accurate time base. there are six registers related to the timer/event counter operating mode. tmrah ([20h]), tmral ([21h]), tmrc ([22h]), tmrbh ([23h]), tmrbl ([24h]) and adcr ([25h]). writing to tmrbl only writes the data into a low byte buffer, and writing to tmrbh will write the data and the contents of the low byte buffer into the time/event counter preload register (16-bit) simultaneously. the timer/event counter preload register is changed by writing to tmrbh operations and writing to tmrbl will keep the timer/event counter preload register unchanged. reading tmrah will also latch the tmral into the low byte buffer to avoid false timing problem. reading tmral returns the contents of the low byte buffer. in other words, the low byte of the timer/event counter can not be read directly. it must read the tmrah first to make the low byte contents of timer/event counter be latched into the buffer. the tmrc is the timer/event counter control register, which defines the timer/event counter options. the timer/event counter control register defines the operat - ing mode, counting enable or disable and active edge. writing to timer b location puts the starting value in the timer/event counter preload register, while reading timer a yields the contents of the timer/event counter. timer b is the timer/event counter preload register. the tm0 and tm1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source (a/d clock) comes from an external (rcin) pin. the timer mode functions as a normal timer with the clock source coming from the internal clock (f sys ). finally, the pulse width measure - ment mode can be used to count the high or low level duration of the external signal (a/d clock from pad:rcin). the counting is based on the system clock (f sys ). in the event count, a/d clock or internal timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter (tmrah and tmral) to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register (tmrbh and tmrbl) and at the same time generates the corresponding interrupt request flag (tf; bit 4 of intc). in the pulse width measurement mode with the ton and te bits equal to one, once the rcin has received a transient from low to high (or high to low if the te bit is 0) it will start counting until the a/d clock returns to the original level and resets the ton. the measured result will remain in the timer/event counter even if the acti- vated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton,
HT47C06L rev. 1.00 13 june 15, 2007 bit no. label function 0~2 unused bit, read as 0 3te defines the tmr active edge of the timer/event counter: in event counter mode (tm1,tm0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (tm1,tm0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 ton to enable/disable timer counting (0=disabled; 1=enabled) 5 6 tm0 tm1 to define the operating mode (tm1, tm0) 10=timer mode (internal clock: f sys ) 01=event counter mode (external clock: a/d clock from pad rcin) 11=pulse width measurement mode (rcin, f sys ) 00=unused 7 unused bit, read as 0 tmrc (22h) register the cycle measurement will function again as long as it receives further transient pulse. note that in this opera - tion mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflow, the counter is re - loaded from the timer/event counter preload register and issues interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will automatically be cleared after the measurement cycle is completed. but in the other two modes, the ton can only be reset by in - structions. in the case of timer/event counter off condi tion, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter turns on, data written to the timer/event counter preload register is kept only in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmrah) is read, the clock will be blocked to avoid errors. as this may re - sults in a counting error, this must be taken into consid - eration. it is strongly recommended to load first the desired value into tmrbl, tmrbh, tmral, and tmrah regis - ters then turn on the related timer/event counter for proper operation. because the in itial value of tmrbl, tmrbh, tmral and tmrah are unknown. example for timer/event counter mode (disable interrupt): clr tmrc clr adcr.1 ; set timer mode clr intc.4 ; clear timer/event counter interrupt request flag mov a, low (65536-1000) ; give timer initial value mov tmrbl, a ; count 1000 time and then overflow mov a, high (65536-1000) mov tmrbh, a mov a, 01010000b ; timer clock source=f sys and timer on mov tmrc, a p10: clr wdt
HT47C06L rev. 1.00 14 june 15, 2007 * ( ! % 6
- # $ % " 1 $ * ( ! % 6

- % & % $ 6 * f 6 6 ( & 6 ' $ ( 8 % 6 b 5 % # 6 * - 6 ( # 6 6 ! ) % 6 + 6 * ( ! % 6 g
6 = * - > 6 6 6 b 5 % # 6 * - 6 # ) 6 ' 7 ' . 6 & " ' % 6 ( & 6 6 ' 7 ' . 6 ( # 6 * 6 ! ) % 6 + 6 * ( ! % 6 g
6 = * - > f 6 * 6 ( & 6 ; ( $ 6 6 + 6 6 % ( & $ % * 4 & $ % ! 6 7 ' . 6 = + , > * * * " 7 & % 6 : ( ) $ 5 % & " % ! % # $ ) % 6 # $ 7 * * * * * * * = 6
( $ @ > 6 ) % # $ 7 1 . . 9 . 6 7 ' . $ 6
" & $ 6
" & * - rc type a/d converter rc type a/d converter an rc type a/d converter is implemented in the HT47C06L. the a/d converter contains two 16-bit pro - grammable count-up counters and the timer a clock source comes from the system clock (f sys =32khz). the timer b clock source comes from the external rc oscil - lator. the tmral, tmrah, tmrbl, tmrbh are com - posed of the a/d converter when adc/tm bit (bit 1 of adcr register) is 1 . the a/d converter timer b clock source may come from rref~rcin oscillation, rsen~rcin oscillation or rcin external clock input. the timer a clock source is the system clock by setting (tm1, tm0=1, 0). there are six registers related to the a/d converter, i.e., tmrah, tmral, tmrc, tmrbh, tmrbl and adcr. the internal timer clock is input to tmrah and tmral, the a/d clock is input to tmrbh and tmrbl. the ovb/ova bit (bit 0 of adcr register) determines whether timer a or timer b overflows, then the tf bit is set and timer interrupt occurs. when the a/d converter mode timer a or timer b overflows, the ton bit is reset and stop counting. writing tmrah/tmrbh makes the starting value be placed in the timer a or timer b and reading tmrah/tmrbh retrieves the contents of the timer a or timer b. writing tmral/tmrbl only writes the data into a low byte buffer, and writing tmrah/tmrbh will write the data and the contents of the low byte buffer into the timer a or timer b (16-bit) si- multaneously. the timer a or timer b is changed by writ - ing tmrah/tmrbh operations and writing tmral/ tmrbl will keep the timer a or timer b unchanged. reading tmrah/tmrbh will also latch the tmral/tmrbl into the low byte buffer to avoid false timing problem. reading tmral/tmrbl returns the contents of the low byte buffer. in other words, the low byte of timer a or timer b cannot be read directly. it must read the tmrah/tmrbh first to make the low byte con - tents of timer a or timer b be latched into the buffer. the bit2 of adcr decides which resistor and capacitor compose an oscillation circuit and input to tmrbh and tmrbl. the tm0 and tm1 bits of tmrc define the timer a clock source. it is recommended that the timer a clock source use the system clock. when the ton bit (bit 4 of the tmrc) is set to 1 the timer a and timer b will start counting until timer a or timer b overflows, the timer/event counter generates the interrupt request flag (tf ; bit 4 of intc) and the timer a and timer b stop counting and reset the ton bit to 0 at the same time. if the ton bit is 1 , the tmrah, tmral, tmrbh and tmrbl cannot be read or written to. only when the timer/event counter is off and when the instruction mov is used can those four registers be read or writ- ten to.
HT47C06L rev. 1.00 15 june 15, 2007 bit no. label function 0 ovb/ova in the rc type a/d converter mode, this bit is used to define the timer/event counter inter - rupt which comes from timer a or timer b overflow. (0= timer a overflow; 1= timer b overflow) in the timer/event counter mode, this bit is void. 1 adc/tm determines whether the 16-bit timer/event counter or rc type a/d converter is enabled. (0= timer/event counter is enabled; 1= a/d converter is enabled) 2 mode defines the a/d converter operating mode 0= rref~cref oscillation (reference resistor and reference capacitor) 1= rsen~cref oscillation (resistor sensor and reference capacitor) 3 bon low voltage detector disabled/enabled (0=disabled; 1=enabled) 4 blf low voltage flag (0=battery power is good; 1=low battery) 5~7 unused bit, read as 0 adcr (25h) register example for rc type ad converter mode (timer a overflow): clr tmrc clr adcr.1 ; set timer mode clr intc.4 ; clear timers/event counter interrupt request flag mov a, low (65536-1000) ; give timer a initial value mov tmrbl, a ; count 1000 time and then overflow mov a, high (65536-1000) mov tmrbh, a mov a, 00000010b ; rref~cref; set rc type adc mode; set timer a overflow mov adcr, a mov a, 00h ; give timer b initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 01010000b ; timer a clock source=f sys and timer on mov tmrc, a p10: clr wdt snz intc.4 ; polling timer/event counter interrupt request flag jmp p10 clr intc.4 ; clear timer/event counter interrupt request flag ; program continue
HT47C06L rev. 1.00 16 june 15, 2007 example for rc type ad converter mode (timer b overflow): clr tmrc clr adcr.1 ; set timer mode clr intc.4 ; clear timer/event counter interrupt request flag mov a, 00h ; give timer a initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00000011b ; rref~cref; set rc type adc mode; set timer b overflow mov adcr,a mov a, low (65536-1000) ; give timer b initial value mov tmrbl, a ; count 1000 time and then overflow mov a, high (65536-1000) mov tmrbh, a mov a, 00110000b ; timer a clock source=f sys and timer on mov tmrc, a p10: clr wdt snz intc.4 ; polling timer/event counter interrupt request flag jmp p10 clr intc.4 ; clear timer/event counter interrupt request flag ; program continue input/output ports there is an 8-bit bidirectional input/output port in the microcontroller, labeled pa which is mapped to the data memory [12h]. all of these i/o lines can be used as in- put and output operations. for the input operation, these lines are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a, [m] (m=12h). for output operation, all the data is latched and remain unchanged until the output latch is rewritten. each i/o line has its own control register (pac) to con - trol the input/output configuration. with this control reg - ister, cmos output or schmitt trigger input with pull-high resistor structures can be reconfigured dynamically un - der software control. to function as an input, the corre - sponding latch of the control register has to be set as 1 . the pull-high resistor will be exhibited automati - cally. the input sources also depend on the control reg - ister. if the control register bit is 1 , the input will read the pad state ( mov and read-modify-write instruc - tions).if the control register bit is 0 , the contents of the latches will move to internal data bus ( mov and read-modify-write instructions). the input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. for output func - tion, cmos is the only configuration. this control regis - ter is mapped to locations 13h. after a chip reset, these input/output lines remain at high levels (pull-high). each bit of these input/output latches can be set or cleared by set [m].i (m=12h) instruc- tions. some instructions first input data and then follow the output operations. for example, set [m].i , cpla [m] , read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. each bit of the port a has the capability of waking-up the device. the pa0 and pa1 are pin-shared with bz and bz ,re - spectively. if the bz mode is selected, the output signal in output mode of pa0 (or pa1) will be bz (or bz ) signal. the input mode always retain its original functions. the 4khz buzzer output signals (in output mode) are con - trolled by the pa0 and pa1 data registers. the truth ta - ble of pa0/bz and pa1/bz are listed below. pa1 data register pa0 data register pa1, pa0 pad function 0 (clr pa.1) 0 (clr pa.0) pa0=bz, pa1=bz 1 (set pa.1) 0 (clr pa.0) pa0=bz, pa1=0 x 1 (set pa.0) pa0=0, pa1=0 mask option
HT47C06L rev. 1.00 17 june 15, 2007 the pa2 is pin-shared with el carrier signals. if the el carrier output is selected, the output signal in output mode of pa2 will be the el carrier signal. the input mode always remains its original functions. the el carrier out - put signal (in output mode) is controlled by the pa2 data register. the truth table of pa2/el is listed below. pa2 data register pa2 pad function 0 (clr pa.2) pa2=0 1 (set pa.2) pa2=el carrier output 9 2 3 4 & $ % ! 6 : . % @ " 1 % ) 6 $ 6 % ( & $ % h < h
h < h
# $ 7 6
( $ / $ 6
" & : ( $ % 6 # $ 7 6 % ( & $ % 5 ( 1 6 % & % $ % ) 6 # $ 7 6 % ( & $ % : ( $ % 6 $ 6 % ( & $ % $ 6
( $ note: bz and el mode functions are not shown in this diagram 6 ( % 6 ( # 7 6 ( % 6 ( # 7 6 6 + 6 = - 6 & > + 6 = - 6 e & > e - e - el timing (f osc =128khz) lcd display memory the device provides an area of embedded data memory for lcd display. this area is located from 40h to 4dh of the ram at bank 1. bank pointer (bp; located at 04h of the ram) is the switch between the ram and the lcd display memory. when the bp is set as 01h , any data written into 40h~4dh will effect the lcd display. when the bp is cleared to 00h , any data written into 40h~ 4dh means to access the general purpose data mem - ory. the lcd display memory can be read and written to only by indirect addressing mode using mp1. when data is written into the display data area, it is automati - cally read by the lcd driver which then generates the corresponding lcd driving signals. to turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. the figure illus - trates the mapping between the display memory and lcd pattern for the device. / * / / /
/ / /
( $ display memory (bank 1)
HT47C06L rev. 1.00 18 june 15, 2007 lcd driver output the output number of the lcd driver device can be 14 2or13 3 by option (i.e., 1 / 2 duty or 1 / 3 duty). the bias type lcd driver can only be c type. a ca - pacitor mounted between c1 and c2 pins is needed. a capacitor mounted between vcc pin and ground is re - quired. low voltage detect lvd the HT47C06L provides a low voltage detector for bat - tery system application. if the lvd is on and the battery voltage is lower than the specified value, the low voltage flag (blf; bit 4 of adcr register) is set. the specified value may be set as 1.3v
0.05v by changing suitable ex - ternal r lvd for the same lot. the low voltage detector cir - cuit can be turned on or off by writing a 1 or a 0 to bon (bit 3 of adcr register). the blf is invalid when the bon is cleared as 0 . set bon=0 after checking the voltage to prevent from dc current consumption of lvd. 6 ; ( $ 6

6 ; ( $ 6 6 & % ! % # $ & 6 6 & % ! % # $ & 6 7 7 6 & % ! % # $ & 6 6 6 6 6 6 7 7 6 & % ! % # $ & 6 6 6 6 6 6 ! " # $ i 6 6 7 7 6 & % ! % # $ 6 " $ 1 " $ & 6 f 6 f 6 6 ! % % # $ lcd driver output (1 / 2 duty, 1 / 2 bias) note: vcc is 2v dd at normal operation mode. vcc* is v dd with lcd off or reset.
HT47C06L rev. 1.00 19 june 15, 2007 ! " # $ % # $ i 6 i 6 6 7 7 6 & % ! % # $ 6 " $ 1 " $ & 6 6 6 7 7 6 & % ! % # $ & 6 6 & % ! % # $ & 6 6 & % ! % # $ & 6 6 & % ! % # $ & 6 i 6 6 & % ! % # $ & 6 i 6 6 & % ! % # $ & 6 i 6 6 & % ! % # $ & 6 7 7 6 & % ! % # $ & 6 6 6 6 6 6 6 6 6 6 6 6 6 f 6 f 6 6 ! % lcd driver output (1 / 3 duty, 1 / 2 bias) note: vcc is 2v dd at normal operation mode. vcc* is v dd with lcd off or reset.
application circuits HT47C06L rev. 1.00 20 june 15, 2007 9 9 # % 7 e 1 % # & e e e . e

mask option the following shows many kinds of mask options in the HT47C06L. all these options should be def ined in order to en - sure proper system functioning. no. function 1 wdt enable or disable selection. (0=enable; 1=disable) 2 buzzer output frequency selection. there are four types of frequency signals for the buzzer output frequency: f sys /2 2 to f sys /2 5 3 to define the pa0 and pa1 output function. 0=normal output 1=buzzer output. pa0 is bz output, pa1 is bz output. 4 to define the pa2 output function. pa2 is normal output or el carrier output. 5 oscillator/lcd are on or off when cpu halt 0=oscillator/lcd is off at halt 1=oscillator/lcd is on at halt 6 pa0~pa7 pull-high option in input mode (0: enable; 1: disable) 7 lcd common selection. there are two types of selection: 2 common (1 / 2 duty) or 3 common (1 / 3 duty). if the 3 common is selected, the segment output pin seg13 will be set as a common output. 8 lcd driver clock selection. there are four types of frequency signals for the lcd driver circuits: f sys /2 3 to f sys /2 6 .
instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none HT47C06L rev. 1.00 21 june 15, 2007
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. HT47C06L rev. 1.00 22 june 15, 2007
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 23 june 15, 2007
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 24 june 15, 2007
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 25 june 15, 2007
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 26 june 15, 2007
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 27 june 15, 2007
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 28 june 15, 2007
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 29 june 15, 2007
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 30 june 15, 2007
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 31 june 15, 2007
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 32 june 15, 2007
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 33 june 15, 2007
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 34 june 15, 2007
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c HT47C06L rev. 1.00 35 june 15, 2007
package information 44-pin qfp (10 10) outline dimensions symbol dimensions in mm min. nom. max. a13 13.40 b 9.90 10.10 c13 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.10 j 0.73 0.93 k 0.10 0.20 0 7 HT47C06L rev. 1.00 36 june 15, 2007
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HT47C06L rev. 1.00 37 june 15, 2007 copyright 2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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